Method For Wafer Thinning Process to Decrease the Failure Rate on Split Gate NOR Flash Product

ABSTRACT

A method for wafer thinning process to decrease the failure rate on split gate NOR flash product of the present invention, wherein comprising the following step: a method for wafer thinning process to decrease the failure rate on Split gate NOR flash product, characterized in that including the following steps: Step 1, place the wafer on the chuck and face up the side which needs to grind; Step 2, fix the wafer on the chuck; Step 3, grind the side of wafer which needs to be grinded by a grinding wheel, said grinding wheel and said chuck rotate at the same time during the grinding process; Step 4, clean up the surface of the wafer when the process of grinding is end; Step 5, enter the next process directly without polishing the wafer which has already complete the grinding process. With the use of the method for wafer thinning process to decrease the failure rate on split gate NOR flash product of the present invention, we may optimize the wafer thinning process conditions effectively and grinding by 8000 mesh grinding wheel without polishing and reduce the failure rate on the finished flash product caused by the flash program disturb to 0% at the same time.

FIELD OF THE INVENTION

The present invention is related to a thinning process method of semiconductor chip, especially a method for wafer thinning process to decrease the failure rate on split gate NOR flash product.

BACKGROUND OF THE INVENTION

Split gate NOR flash product is widely used in the embedded memory product. So it has a high requirement on the flash yield as any tiny failure in the coding region is not permitted.

The special structure of split gate NOR flash product: four word lines(WL) concurrent sharing a SourceLine (SL). Such structure tend to cause the background transfer service which needn't programmed be disturbed by programming as the SourceLine shared by four word lines has been put in high potential (10.5V) when the flash is programming by page.(illustrated as FIG. 1)

Studies have shown that the flash bytes which suffered from the program disturb is mainly the bytes that don't share WL. The mechanism of program disturb is the reverse tunneling program disturb.

Although the wafer have passed program operation on every bits in the stage of CP, still the flash limited margin of the anti-program disturb will consumed as the chip may be affected by external mechanical forces and the electric field when thinning and packaging in the back end. It may lead to the program disturb failure of the finished flash.

Nowadays applications of many products require the package of chip should be smaller and more exquisite, and the thickness is even required be less than 150 micron, while the traditional process method of wafer thinning and polishing will weaken the anti-program disturb ability of the split gate NOR flash product to a large extent. 2000 or 5000 mesh grinding wheel and the polishing process cannot meet the product yield of chip. Thus, to seek an optimized condition of wafer thinning process is absolutely vital to the final product yield.

SUMMARY OF THE INVENTION

The present invention disclosed a method for wafer thinning process to decrease the failure rate on split gate NOR flash product in order to solve the defect in the existing technology. Such as flash limited margin of the anti-program disturb will consumed as the chip may be affected by external mechanical forces and the electric field when thinning and packaging in the back end. And it may lead to the program disturb failure of the finished flash product.

In order to achieve the target, the technology solution of embodiments of the invention are: A method for wafer thinning process to decrease the failure rate on split gate NOR flash product, that includes the following steps:

Step 1: place the wafer on the chuck and face up the side which needs to grind;

Step 2: fix the wafer on the chuck;

Step 3: grind the side of wafer which needs to be grinded by a grinding wheel, said grinding wheel and said chuck rotate at the same time during the grinding process;

Step 4: clean up the surface of the wafer when the process of grinding is end;

Step 5: enter the next process directly without polishing the wafer which has already complete the grinding process.

In a further embodiment of the invention, the process method described above further includes a structure wherein the diameter of a grinding wheel is greater than the diameter of the wafer, and the grinding wheel covers the surface of the wafer.

In a further embodiment of the invention, the process method mentioned above further includes a grinding wheel that is parallel to the chuck.

In a further embodiment of the invention, the process method mentioned above further includes using a grinding wheel and a chuck that rotate in different directions.

In a further embodiment, the process method mentioned above is practiced wherein the grinding wheel is at least 8000 mesh.

In a further embodiment of the invention, the process method mentioned above, is practiced and the impurity left is cleared up by coolant when grinding in step 3.

In a further embodiment the method is practiced wherein the thickness of said wafer grinded is 150 um in Step 4.

In a further embodiment, a method for wafer thinning process to decrease the failure rate on split gate NOR flash product of the present invention will have the following effect after applying the scheme above: (1) Optimize the wafer thinning process conditions effectively and grinding by 8000 mesh grinding wheel without polishing; (2) Reduce the failure rate on the finished flash product caused by the flash program disturb to 0% at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features, objects and advantages of the invention will become more apparent by reading the detailed description of the non-limiting embodiment with reference to the following drawings.

FIG. 1 illustrates the special structure diagram of split gate NOR flash product;

FIG. 2 is a flow diagram of a method for wafer thinning process to decrease the failure rate on split gate NOR flash product;

FIG. 3 is a structure diagram of the equipment for a method for wafer thinning process to decrease the failure rate on split gate NOR flash product;

FIG. 4 is a diagram of the grinding wafer in a method for wafer thinning process to decrease the failure rate on split gate NOR flash product.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The following context will make further description for the specific embodiments of present invention in conjunction with appended drawings in order to make the technical means, features of creativity, the target achieved and the effect of the present invention easier to understand. Reference sequence is as follows: wafer 1, chuck 2, grinding wheel 3.

As illustrated as FIG. 3A, in an embodiment of the present invention, a method for wafer thinning process to decrease the failure rate on split gate NOR flash product, includes the following steps:

Step 1: place the wafer 1 on the chuck 2 and face up the side which needs to grind;

Step 2: fix the wafer 1 on the chuck 2;

Step 3: grind the side of wafer 1 which needs to be grinded by a grinding wheel 3, grinding wheel 3 and chuck 2 rotate at the same time during the grinding process;

Step 4: clean up the surface of the wafer 1 when the process of grinding is end;

Step 5: enter the next process directly without polishing the wafer 1 which has already complete the grinding process, for example, to implement wafer saw or other IC assembly process without polishing process. In a wafer saw process, sawing the wafer to form a lot of dies, and the key point in this application is not to implement wafer backside polish after backside grinding while the die is applied on NOR flash device.

In the embodiment of the present invention, wherein the diameter of grinding wheel 3 is longer than diameter of wafer 1, and grinding wheel 3 covers the surface of wafer 1. In a further the embodiment of the present invention, grinding wheel 3 is parallel to chuck 2.

In an embodiment of the present invention, the grinding wheel 3 and chuck 2 rotates in different direction. In a further embodiment of the present invention, the grinding wheel 3 is at least 8000 mesh. In an embodiment of the present invention, the impurity left is cleared up by coolant when grinding in step 3. In a further embodiment of the present invention, the thickness of wafer grinded is 150 um, so the failure rate on the finished flash product caused by the flash program disturb will be 0%. Furthermore, if the thickness of wafer grinded is 150 um, the failure rate on the finished flash product caused by the flash program disturb will be 0.38%.

In an embodiment of the present invention, first wafer 1 is fixed on the chuck 2, next the wafer 1 is ground using a 8000 mesh grinding wheel, then dry the water stains on the surface of the wafer by a hot hair dryer after grinding and put the wafer 1 into the next step without polishing.

In conclusion, a method for wafer thinning process to decrease the failure rate on split gate NOR flash product of the present invention optimized the wafer thinning process conditions effectively and grinding by 8000 mesh grinding wheel without polishing, which could reduce the failure rate on the finished flash product caused by the flash program disturb to 0% at the same time.

The context above described the embodiment of the invention. While what should be noticed is that the present invention is not limited by the specific implementations mentioned above. The equipment and the structure that not have been detailed described should be regarded as the ordinary way to implement in the art; any modifications and substitutions by those ordinarily skilled in the field of the invention will not affect the substance of the invention. 

I claim:
 1. A method for wafer thinning process to decrease the failure rate on Split gate NOR flash product, characterized by the following steps: Step 1, place the wafer on the chuck and face up the side which needs to grind; Step 2, fix the wafer on the chuck; Step 3, grind the side of wafer which needs to be grinded by a grinding wheel, said grinding wheel and said chuck rotate at the same time during the grinding process; Step 4, clean up the surface of the wafer when the process of grinding is end; Step 5, enter the next process directly without polishing the wafer which has already complete the grinding process.
 2. The method of claim 1, wherein the diameter of said grinding wheel is longer than said diameter of said wafer, and said grinding wheel covers the surface of said wafer.
 3. The method of claim 1, wherein said grinding wheel is parallel to said chuck.
 4. The method of claim 1, wherein said grinding wheel and said chuck rotates in different directions.
 5. The method of claim 1, wherein said grinding wheel is at least 8000 mesh.
 6. The method of claim 1, wherein the impurity left is cleared up by coolant when grinding in step
 3. 7. The method of claim 1, wherein the thickness of said wafer grinded is 150 um in Step
 4. 